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| DATA SHEET MOS INTEGRATED CIRCUIT MC-4516DC72 16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Description The MC-4516DC72 is a 16,777,216 words by 72 bits synchronous dynamic RAM module on which 18 pieces of 64M SDRAM : PD4564841 are assembled. This module provides high density and large quantities of memory In a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features * 16,777,216 words by 72 bits organization (ECC type) * Clock frequency and Clock access time Family /CAS Latency Clock frequency (MAX.) MC-4516DC72-A10 CL = 3 CL = 2 MC-4516DC72-A12 CL = 3 CL = 2 MC-4516DC72-A10B CL = 3 CL = 2 100 MHz 67 MHz 83 MHz 55 MHz 100 MHz 67 MHz Burst cycle time (MIN.) 10 ns 15 ns 12 ns 18 ns 10 ns 15 ns Power consu mption (MAX.) Active 5.454 W 5.292 W 5.130 W 4.968 W 5.616 W 5.292 W 68.4 mW (CMOS level input ) Standby 130 mW (CMOS level input ) Z * Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Quad internal banks controlled by BA0 and BA1 (Bank Select) * Programmable burst-length (1, 2, 4, 8 and Full Page) * Programmable wrap sequence (Sequential / Interleave) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * Single +3.3 V +0.3 / -0.15 V power supply * LVTTL compatible * 4,096 refresh cycles/64 ms * Burst termination by Burst Stop command and Precharge command * 200-pin dual in-line memory module (Pin pitch = 1.27 mm) * Registered type * Serial PD The information in this document is subject to change without notice. Document No. M12351EJ4V0DS00 (4th edition) Date Published May 1998 NS CP(K) Printed in Japan The mark Z shows major revised points. (c) 1997 MC-4516DC72 Ordering Information Part number MC-4516DC72F-A10 Clock frequency 100 MHz 83 MHz 100 MHz Package Mounted devices 200-pin Dual In-line Memory Module 18 pieces of 64M SDRAM : PD4564841G5 (Socket Type) Edge connector : Gold plated [Double side] (400 mil TSOP (II)) Z MC-4516DC72F-A12 MC-4516DC72F-A10B 2 MC-4516DC72 Pin Configuration 200-pin Dual In-line Memory Module Socket Type (Edge connector : Gold plated) [MC-4516DC72F] 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 NC NC VSS NC NC NC NC DQ 71 DQ 70 VSSQ DQ 69 DQ 68 VCCQ NC VSS NC DQ 59 DQ 58 VSSQ DQ 57 DQ 56 VCCQ DQ 55 DQ 54 VSSQ DQ 53 DQ 52 VCCQ DQ 47 DQ 46 VSSQ DQ 45 DQ 44 VCCQ DQ 39 DQ 38 VSS DQ 37 DQ 36 VCC A6 A7 VSS BA0(A13) NC VCC DQM /WE VSS NC CLK0 VCC /CS1 /CS0 VSS BA1(A12) A10 VCC A2 A3 VSSQ DQ 31 DQ 30 VCCQ DQ 29 DQ 28 VSSQ DQ 23 DQ 22 VCCQ DQ 21 DQ 20 VSSQ NC NC VCCQ NC VSS VSSQ NC NC VCCQ DQ 11 DQ 10 VSSQ DQ 9 DQ 8 VCCQ DQ 3 DQ 2 VSS DQ 1 DQ 0 SDA SA0 SA1 SA2 VCC NC NC VCC NC NC IN OUT NC NC VSS DQ 67 DQ 66 VCCQ DQ 65 DQ 64 VSSQ DQ 63 DQ 62 NC DQ 61 DQ 60 VCCQ NC NC VSSQ NC NC VCCQ DQ 51 DQ 50 VSSQ DQ 49 DQ 48 VCCQ DQ 43 DQ 42 VSSQ DQ 41 DQ 40 VCCQ A4 A5 VSSQ A8 A9 VCC CKE1 CKE0 VSS /CAS NC VCC VSS /RAS VSS NC A11 VCC A0 A1 VSS DQ 35 DQ 34 VCCQ DQ 33 DQ 32 VSSQ DQ 27 DQ 26 VCCQ DQ 25 DQ 24 VSSQ DQ 19 DQ 18 VCCQ DQ 17 DQ 16 VSSQ NC NC VCCQ DQ 15 DQ 14 VSSQ DQ 13 DQ 12 VCCQ DQ 7 DQ 6 VSSQ DQ 5 DQ 4 VCCQ NC NC NC NC NC SCL NC VSSQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 /xxx indicates active low signal. A0 - A11 : Address Inputs [Row : A0 - A11, Column : A0 - A8] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ71 CLK0 CKE0, CKE1 /CS0, /CS1 /RAS /CAS /WE DQM IN, OUT SA0 - SA2 SDA SCL VCC VCCQ VSS VSSQ NC : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Unbuffered Physical Detect Input/Output (separate) : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Power Supply for Data Input/Output : Ground : Ground for Data Input/Output : No Connection 3 MC-4516DC72 Block Diagram FEEDBACK /CS0, CKE0 /CS1, CKE1 /RAS /CAS /WE DQM A0 - A11, BA0, BA1 REGISTER 10CLK PLL CLOCK BUFFER CLK0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D1 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D2 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D11 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D12 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D3 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D4 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D13 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D14 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D5 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D6 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D15 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D16 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D7 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D8 DQ 64 DQ 65 DQ 66 DQ 67 DQ 68 DQ 69 DQ 70 DQ 71 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D17 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D18 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 D9 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 SERIAL PD SCL D10 SDA A0 A1 A2 SA0 SA1 SA2 Vcc C Vss D1 - D18, REGISTER, PLL CLOCK BUFFER D1 - D18, REGISTER, PLL CLOCK BUFFER Remarks 1. A 10 5 % resistor shall be wired in series with DQ0 - DQ71 near the card edge connector. All clock line outputs from the PLL CLOCK BUFFER shall be equal length. 2. D1 - D18 : PD4564841 (2M words x 8 bits x 4 banks) 4 MC-4516DC72 Electrical Specifications * All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 21 0 to +70 -55 to +125 Unit V V mA W C C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.15 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 + 0.8 70 Unit V V V C Capacitance (TA = 25 C, f = 1 MHz) Parameter Input capacitance Symbol CI1 CI2 Data input/output capacitance CI/O Test condition A0 - A11, BA0, BA1, CKE0, CKE1, /CS0, /CS1, /RAS, /CAS, /WE, DQM CLK0 DQ0 - DQ71 MIN. TYP. MAX. 15 8 15 pF Unit pF 5 MC-4516DC72 DC Characteristics (Recommended Operating Conditions unless otherwise noted) [ MC-4516DC72-A10, 4516DC72-A12 ] Parameter Operating current Symbol ICC1 Test condition Burst length = 1, tRC tRC(MIN.) , IO = 0 mA /CAS latency = 3 /CAS latency = 2 -A10 -A12 -A10 -A12 Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P ICC2PS ICC2N ICC2NS Active standby current in power down mode Active standby current in non power down mode ICC3NS Operating current (Burst mode) /CAS latency = 3 ICC4 ICC3P ICC3PS ICC3N CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK(MIN.) , IO = 0 mA /CAS latency = 2 -A10 -A12 -A10 -A12 Refresh current ICC5 tRC tRC(MIN.) /CAS latency = 2 -A10 -A12 /CAS latency = 3 -A10 -A12 Self refresh current Input leakage current Output leakage current High level output voltage Low level output voltage ICC6 II(L) IO(L) VOH VOL CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V DOUT is disabled, VO = 0 to 3.6 V IO = - 2.0 mA IO = + 2.0 mA -10 -10 2.4 0.4 180 1,245 1,155 1,470 1,380 1,470 1,380 1,515 1,425 36 +10 +10 mA 2 mA 4 mA 3 MIN. MAX. 1,155 1,110 1,200 1,155 54 36 360 108 90 72 450 mA 2 mA 2 mA 2 mA 2 Unit mA Notes 1 A A V V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. VCC - 0.2 V VIH(CLK) VIH(MAX.), 0 V VIL 0.2 V 3. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 4. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.). 6 MC-4516DC72 Z [ MC-4516DC72-A10B ] Parameter Operating current Symbol ICC1 Test condition Burst length = 1, tRC tRC(MIN.) , IO = 0 mA Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P ICC2PS ICC2N ICC2NS Active standby current in power down mode Active standby current in non power down mode ICC3NS Operating current (Burst mode) Refresh current ICC5 tRC tRC(MIN.) ICC4 ICC3P ICC3PS ICC3N CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. CKE VIL(MAX.), tCK = 15 ns CKE VIL(MAX.), tCK = CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK(MIN.) , IO = 0 mA /CAS latency = 2 /CAS latency = 3 /CAS latency = 2 /CAS latency = 3 Self refresh current Input leakage current Output leakage current High level output voltage Low level output voltage ICC6 II(L) IO(L) VOH VOL CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V DOUT is disabled, VO = 0 to 3.6 V IO = - 4.0 mA IO = + 4.0 mA -10 -3 2.4 0.4 180 1,155 1,470 1,470 1,560 218 +10 +3 mA 2 mA 4 mA 3 /CAS latency = 2 /CAS latency = 3 MIN. MAX. 1,110 1,200 218 19 560 108 290 72 650 mA 2 mA 2 mA 2 mA 2 Unit mA Notes 1 A A V V Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. VCC - 0.2 V VIH(CLK) VIH(MAX.), 0 V VIL 0.2 V 3. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 4. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.). 7 MC-4516DC72 AC Characteristics (Recommended Operating Conditions unless otherwise noted) AC Characteristics Test Conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). * An access time is measured at 1.4 V. tCK tCH CLK 2.0 V 1.4 V 0.8 V tSETUP tHOLD 2.0 V 1.4 V 0.8 V tAC tOH Output tCL Input 8 MC-4516DC72 Synchronous Characteristics [ MC-4516DC72-A10, 4516DC72-A12 ] Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 Input CLK duty cycle Data-out hold time Data-out low-impedance time Data-out high-impedance time Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0, /CS1, /RAS, /CAS, /WE, DQM) setup time Command (/CS0, /CS1, /RAS, /CAS, /WE, DQM) hold time tCK3 tCK2 tAC3 tAC2 - tOH tLZ tHZ tDS tDH tAS tAH tCKS tCKH tCKSP tCMS tCMH 40 2.5 0 3.5 3.0 1.5 3.5 0.5 3.5 0.5 3.0 3.5 0.5 8.0 10 15 -A10 MAX. (100 MHz) (67 MHz) 8.5 9.5 60 40 2.5 0 3.5 3.5 2.0 3.5 0.5 3.5 0.5 3.5 3.5 0.5 8.0 MIN. 12 18 -A 12 MAX. (83 MHz) (55 MHz) 9.5 11.5 60 ns ns ns ns % ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Unit Note Note 1. Output load 1.4 V Z = 50 Output 50 pF 50 9 MC-4516DC72 Z [ MC-4516DC72-A10B ] Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 Input CLK duty cycle Data-out hold time Data-out low-impedance time Data-out high-impedance time /CAS latency = 3 /CAS latency = 2 Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0, /CS1, /RAS, /CAS, /WE, DQM) setup time Command (/CS0, /CS1, /RAS, /CAS, /WE, DQM) hold time tCK3 tCK2 tAC3 tAC2 - tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS tCMH 40 2.5 0 2.5 2.5 3.0 1.5 3.5 0.5 3.5 0.5 3.0 3.5 0.5 7.5 8.5 10 15 -A10B MAX. (100 MHz) (67 MHz) 7.5 8.5 60 ns ns ns ns % ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Unit Note Note 1. Output load 1.4 V Z = 50 Output 50 pF 50 10 MC-4516DC72 Asynchronous Characteristics [ MC-4516DC72-A10, 4516DC72-A12 ] Parameter Symbol MIN. REF to REF/ACT command period ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command period (Auto precharge) Mode register set cycle time Transition time Refresh time /CAS latency = 3 /CAS latency = 2 tRC tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF 100 60 30 30 20 -1CLK + 10 1CLK + 30 30 20 1 30 64 120,000 -A10 MAX. MIN. 120 72 36 36 24 -1CLK + 12 1CLK + 30 30 20 1 30 64 120,000 -A12 MAX. ns ns ns ns ns ns ns ns ns ns ms Unit Note Z [ MC-4516DC72-A10B ] Parameter Symbol MIN. REF to REF/ACT command period ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command period (Auto precharge) Mode register set cycle time Transition time Refresh time /CAS latency = 3 /CAS latency = 2 tRC tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF 90 60 30 30 20 10 1CLK + 30 1CLK + 30 2 1 30 64 120,000 -A10B MAX. ns ns ns ns ns ns ns ns CLK ns ms Unit Note 11 MC-4516DC72 Relationship between Frequency and Latency [ MC-4516DC72-A10, 4516DC72-A12 ] Speed version Clock cycle time [ns] 10 100 3+1 3 7 10 6 2 3 0 4 -A 10 15 67 2+1 2 5 7 4 2 2 0 2 12 83 3+1 3 7 9 6 2 3 0 4 -A 12 18 55 2+1 2 5 6 4 2 2 0 2 Z Frequency [MHz] /CAS latency + 1 cycle [tRCD] /RAS latency (/CAS latency + [tRCD]) [tRC] [tRAS] [tRRD] [tRP] [tDPL] [tDAL] Remark All internal signals (A0 - A11, BA0, BA1, /CS0, /CS1, CKE0, CKE1, /RAS, /CAS, /WE, DQM) from register are delayed by one cycle. Therefore, DQ is delayed by one cycle. Z [ MC-4516DC72-A10B ] Speed version Clock cycle time [ns] Frequency [MHz] /CAS latency + 1 cycle [tRCD] /RAS latency (/CAS latency + [tRCD]) [tRC] [tRAS] [tRRD] [tRP] [tDPL] [tDAL] 10 100 3+1 3 7 9 6 2 3 0 3 -A 10B 15 67 2+1 2 5 6 4 2 2 0 2 Remark All internal signals (A0 - A11, BA0, BA1, /CS0, /CS1, CKE0, CKE1, /RAS, /CAS, /WE, DQM) from register are delayed by one cycle. Therefore, DQ is delayed by one cycle. 12 MC-4516DC72 Serial PD [ MC-4516DC72-A10, 4516DC72-A12 ] Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width Data width (continued) Voltage interface CL = 3 Cycle time -A10 -A12 10 CL =3 Access time -A10 -A12 11 12 13 14 15 16 17 18 19 20 21 22 23 DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time -A10 -A12 24 CL = 2 Access time -A10 -A12 25 - 26 27 tRP(MIN.) -A10 -A12 28 tRRD(MIN.) -A10 -A12 29 tRCD(MIN.) -A10 -A12 30 tRAS(MIN.) -A10 -A12 Hex 80H 08H 04H 0CH 09H 02H 48H 00H 01H A0H C0H 85H 95H 02H 80H 08H 08H 01H 8FH 04H 06H 01H 01H 16H 1EH F0H 30H 95H B5H 00H 1EH 24H 14H 18H 1EH 24H 3CH 48H Bit 7 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 Bit 5 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 1 1 Bit 2 0 0 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 Bit 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 Bit 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 30 ns 36 ns 20 ns 24 ns 30 ns 36 ns 60 ns 72 ns 15 ns 18 ns 9.5 ns 11.5 ns (1/2) Notes 128 bytes 256 bytes SDRAM 12 rows 9 columns 2 banks 72 bits 0 LVTTL 10 ns 12 ns 8.5 ns 9.5 ns ECC Normal x8 x8 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0 Registered 13 MC-4516DC72 [ MC-4516DC72-A10, 4516DC72-A12 ] Byte No. 31 32-61 62 63 SPD revision Checksum for bytes 0 - 62 -A10 -A12 64-71 72 73 - 90 91 - 92 93 - 94 95 - 98 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number Mfg specific 00H 00H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Described Module bank density Hex 20H 00H 01H A5H 51H Bit 7 0 0 0 1 0 Bit 6 0 0 0 0 1 Bit 5 1 0 0 1 0 Bit 4 0 0 0 0 1 Bit 3 0 0 0 0 0 Bit 2 0 0 0 1 0 Bit 1 0 0 0 0 0 Bit 0 0 0 1 1 1 1 (2/2) Notes 128 M bytes Z Z 99 -125 126 127 14 MC-4516DC72 Z [ MC-4516DC72-A10B ] Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 - 26 27 28 29 30 tRP(MIN.) tRRD(MIN.) tRCD(MIN.) tRAS(MIN.) Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of module banks Data width Data width (continued) Voltage interface CL = 3 Cycle time CL =3 Access time DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time CL = 2 Access time Hex 80H 08H 04H 0CH 09H 02H 48H 00H 01H A0H 75H 02H 80H 08H 08H 01H 8FH 04H 06H 01H 01H 16H 1EH F0H 85H 00H 1EH 14H 1EH 3CH Bit 7 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 Bit 4 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 1 Bit 2 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 1 1 1 Bit 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 Bit 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 0 (1/2) Notes 128 bytes 256 bytes SDRAM 12 rows 9 columns 2 banks 72 bits 0 LVTTL 10 ns 7.5 ns ECC Normal x8 x8 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0 Registered 15 ns 8.5 ns 30 ns 20 ns 30 ns 60 ns 15 MC-4516DC72 Z [ MC-4516DC72-A10B ] Byte No. 31 32-61 62 63 64-71 72 73 - 90 91 - 92 93 - 94 95 - 98 99 -125 126 127 SPD revision Checksum for bytes 0 - 62 Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number Mfg specific 00H 00H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Described Module bank density Hex 10H 00H 01H 75H Bit 7 0 0 0 0 Bit 6 0 0 0 1 Bit 5 0 0 0 1 Bit 4 1 0 0 1 Bit 3 0 0 0 0 Bit 2 0 0 0 1 Bit 1 0 0 0 0 Bit 0 0 0 1 1 1 (2/2) Notes 64 M bytes 16 AC Parameters for Read Timing (Burst length = 2, /CAS latency = 2) T0 tCK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 ,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,,, ,,, ,,,,, ,,, ,,,,,, ,,, ,,,, ,,,,, ,,, ,,, ,,,,, ,,, ,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,, ,,, ,,,, ,,, ,,,, ,,, ,,,, ,,, ,,,, ,,, ,,,,, ,,, CLK tCH tCL CKE tCKS tCMS tCMH Auto Precharge Start for Bank D tCKH /CS /RAS /CAS /WE BA0 BA1 A10 ADD tAS tAH DQM DQ L tAC tAC Hi-Z tRCD tLZ tOH tOH tRRD tHZ tRAS tRC tRP MC-4516DC72 Bank A activate command Bank A precharge command Bank A activate command Bank D activate command Bank D read command with auto precharge Bank A read command 17 Remark All internal signals (A0 - A11, BA0, BA1, /CS0, CKE0, /RAS, /CAS, /WE, DQM) from register are delayed by one cycle. Therefore, DQ is delayed by one cycle. 18 CLK CKE /CS /RAS /CAS /WE BA0 BA1 A10 ADD DQM DQ AC Parameters for Write Timing (Burst length = 4, /CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 ,,, ,, ,,,,, ,,, ,,,,, ,,,, ,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,,,, ,,, ,,, ,,, ,,,,, ,,,,, ,,,,, ,,,,, tCKS tCMS tCMH Auto Precharge Start for Bank A Auto Precharge Start for Bank D tCKH tAS tAH L tDS tDH Hi-Z tRCD tRRD tRC tDAL tDPL tRP MC-4516DC72 Bank D activate command Bank D write command with auto precharge Remark All internal signals (A0 - A11, BA0, BA1, /CS0, CKE0, /RAS, /CAS, /WE, DQM) from register are delayed by one cycle. Therefore, DQ is delayed by one cycle. Bank A activate command Bank A write command with auto precharge Bank A precharge command Bank A activate command Bank A write command without auto precharge Bank A activate command MC-4516DC72 Package Drawing 200 PIN DUAL IN-LINE MODULE (SOCKET TYPE) A (AREA B) M1 (AREA B) Y Z N R M Q L A H K B I G C A1 (AREA A) D B S U1 U2 T M2 (AREA A) J (OPTIONAL HOLES) E ITEM A A1 B C D MILLIMETERS 153.7 153.70.13 19.05 77.47 6.35 2.0 3.125 26.67 6.35 1.27 (T.P.) 8.905 31.135 83.82 10.0 38.10.13 26.1 12.0 4.0 MAX. 1.0 R2.0 4.000.10 INCHES 6.051 6.051 +0.006 -0.005 0.750 3.050 0.250 0.079 0.123 1.050 0.250 0.050 (T.P.) 0.351 1.226 3.300 0.394 1.5000.006 1.028 0.472 0.158 MAX. 0.039 R0.079 0.157 +0.005 -0.004 detail of A part W detail of B part D2 D1 D2 E G H V X P D1 I J K L M M1 M2 N P Q R S T U1 U2 V W X Y Z 3.0 1.270.1 4.0 MIN. 4.0 MIN. 0.25 MAX. 1.00.05 2.540.10 3.0 MIN. 3.0 MIN. 0.118 0.0500.004 0.157 MIN. 0.157 MIN. 0.010 MAX. 0.039 +0.003 -0.002 0.1000.004 0.118 MIN. 0.118 MIN. M200S-50A9 19 MC-4516DC72 [MEMO] 20 MC-4516DC72 [MEMO] 21 MC-4516DC72 [MEMO] 22 MC-4516DC72 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 23 MC-4516DC72 [MEMO] CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5 |
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